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asix electronics corporation first released date: 11/07/2002 4f, no.8, hsin ann rd., science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-563-9799 http:// www.asix.com.tw ax88655 ab 5-port 10/100/1000base-t ethernet switch 5-port gigabit ethernet switch with embedded memory document no.: AX88655AB / v0.8 / june 11, 2003 features ? 5-port gigabit ethernet switch integrating macs, packet buffer memory and switching engine with rgmii/gmii/mii interface ? rgmii support rev 1.3 with 3.3v io ? full duplex 1000 mbit/s. ? full and half duplex 10/100 mbit/s ? supports auto-sensing or manual selection for speed and duplex capability with an embedded mpu ? store-and-forward operation support ? performs full wire-speed switching with head of line (hol) blocking prevention ? supports up to 8 port-based vlan groups ? supports broadcast storm filtering . ? quality-of-service provisi oning on 802.1p tag and port-pairs with two priority queues ? by-port egress/ingress bandwidth (rate) control ? embedded 128k byte sram for packet buffer ? supports packet length up to 1522 bytes ? supports 9k/12k byte jubmo packet ? integrated two-way address-lookup engine and table for 4k mac addresses ? programmable aging mechanism for the two-way 4k mac addresses table ? two hashing schemes: direct and xor mode. ? support ingress port security mode, incoming packets with unknown source mac address could be dropped ? egress/ingress port mirro ring for sniffer function . ? flow control - full-duplex ieee 802.3x flow control - half-duplex back pressure flow control - optional smart flow control for mix-speed connection ? supports port-based trunking for high-bandwidth links ? provides 5 gpio ports ? provides eeprom interface for auto-configuration ? system clock input is one 25mhz crystal and one 125mhz from phy gclk output ? 1.8 and 3.3v operations ? 3.3 i/os and packaged in 272-pin bga product description the AX88655AB is an 5-port 10/100/1000 m bps ethernet switch with, gmii/rg mii or mii interface. the switch controller provides network system manufacturers the ideal platform for building smart and cost-effective backbone switches for small to medium sized businesses. the AX88655AB 5-port 10/100/100 base-t single chip switch controllers combine the benefits of network simplicity, flexibility and high integration. its highly integrated feature set enables network system manufacturers to build smart switches for the fast-growing small to medium business market segment. benefits of AX88655AB switches are below. simplicity provides a smart, simple and low maintenance plug-and-play network interconnect system for small to medium size businesses flexibility highly scalable configuration allows system manufacturers to enable or disable a range of features to best meet their target price point. integration highly integrated design drives down overall switch manufacturing costs. target applications 5-port gigabit layer 2 switches for workgroup high-port count layer 2 switches with trunking high performance solution of ethernet backbone
asix electronics corporation 2 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential system block diagram always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electr onics reserves the rights to m odify the product specification wit hout notice. no liability is assumed as a result of the us e of this product. no rights under any pa tent accompany the sale of the product. AX88655AB switch controller eeprom 5 * 10/100/1000mbps phys
asix electronics corporation 3 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential contents 1.0 AX88655AB overview......................................................................................................... ................................5 1.1 g eneral d escription ............................................................................................................................5 1.2 AX88655AB b lock d iagram .............................................................................................5 1.3 p in c onnection d iagram ...................................................................................................................6 2.0 i/o definition............................................................................................................. ..........................................7 2.1 rgmii/gmii/mii i nterface .............................................................................................................7 2.2 m iscellaneous ............................................................................................................................... ...........9 3.0 functional description ..................................................................................................... .......................11 3.1 i ntroduction ............................................................................................................................... .............11 3.2 p acket f iltering and f orwarding p rocess .....................................................................11 3.3 mac a ddress r outing , l earning and a ging p rocess .............................................11 3.4 f ull d uplex 802.3 x f low c ontrol .........................................................................................11 3.5 h alf d uplex b ack p ressure c ontrol ..................................................................................11 3.6 mii p olling ............................................................................................................................... .................11 3.7 p ort -b ased q o s: p ort -p air .........................................................................................................11 3.8 vlan and b roadcast s torming p revention ................................................................12 3.9 s ecurity o peration - p ort sa restriction .....................................................................12 3.10 i ngress /e gress b andwidth c ontrol s cheme .............................................................12 3.11 p ort m irroring ............................................................................................................................... .....12 4.0 register descriptions ...................................................................................................... ..........................13 5.0 electrical specification and timing........................................................................................ .......21 5.1 a bsolute m aximum r atings ........................................................................................................21 5.2 g eneral o peration c onditions .................................................................................................21 5.3 dc c haracteristics ............................................................................................................................21 5.4 ac specifications ............................................................................................................................... ...22 6.0 package information ........................................................................................................ .........................27 appendix a: system applications ................................................................................................ ...............30 appendix b: design note........................................................................................................ ............................31 appendix c: weight setting for qos ............................................................................................. ...........32 appendix d: resolution ingress/eg ress for bandwidth control .......................................32
asix electronics corporation 4 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential figures f ig -1 AX88655AB b lock d iagram ............................................................................................................................... .5 f ig -2 t op v iew of AX88655AB ab p in d iagram .........................................................................................................6
asix electronics corporation 5 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 1.0 AX88655AB overview 1.1 general description the AX88655AB gigabit switch controller supports eight 10/100/1000 mbps ports in wire-speed operation. the AX88655AB gigabit switch controller provide s eight 10/100/1000 ethe rnet ports with rgmii/gm ii/mii interface. for each ports, the AX88655AB supports gmii/rgmii (802.3ab, 1000base-t) interface with full-duplex operation at gigabit speed, full- or half-duplex operation at 10/100 mbps speed (using 802.3/u, 10/100base-t) and polls the status of phys with an embedded mpu. the device supports 4k internal mac addresses which are shared by all ports with an embedded sram. the learning/routing engine is implemented with a two-way ha sh/linear algorithm to reduce possibility of routing collision. basically the AX88655AB supports non-blocking wire speed forwarding rate and no head-of-line (hol) blocking issue. the AX88655AB provides two flow-control mechanisms to avoid loss of data: an optional jamming based backpressure flow control in the half-duplex operation and i eee 802.3x in the full-duplex mode. to support quality of service (qos), each output port has two priority queues a nd their assignment can be based on the 802.1p priority field or port-pair setti ng. each output port retrieves the frame s from the shared buffer based on queuing and sends them to the transmitting (tx) fifo. 1.2 AX88655AB block diagram fig-1 AX88655AB block diagram 10/100/1000 mac 10/100/1000 mac 10/100/1000 mac 10/100/1000 mac high speed switch fabric routing /learning engine buffer manager packet buffer general purpose i/o interface (gpio) address look-up table 10/100/1000 mac eeprom interface gpio configuration logic rgmii/gmii phy rgmii/gmii phy rgmii/gmii phy rgmii/gmii phy rgmii/gmii phy
asix electronics corporation 6 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 1.3 pin connection diagram fig-2 top view of AX88655ABb pin diagram
asix electronics corporation 7 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 2.0 i/o definition the following terms describe the AX88655AB pin-out: all pin names with the ?/? suffix are asserted low. the following abbreviations are used in following tables. i input pu pull up o output pd pull down i/o input/output p power pin od open drain 2.1 rgmii/gmii/mii interface 2.1.1 rgmii/gmii/mii interface port 0 signal name i/o pin no. description gtx_clk0 o y2 125mhz clock output: it is a continuous 125 mhz clock output to giga-phy operating at 1000base-t. that is, it is a timing reference for tx_en0 and txd0[7:0] tx_en0 o y1 transmit enable: when tx_en0 is asserted, data on txd0[7:0] are transmitted onto phy. tx_en0 is synchronous to gtx_clk0 in 1000base-t mode and synchronous to tx_clk0 in 10/100base-t mode. txd0[7:0] o w1, v2, v1, u3, u2,u1 , t2, t1 transmit data: synchronous to the rising of gtx_clk0 in 1000base-t mode. and synchronous to rising edge of tx_clk0 in 10/100base-t mode., for rgmii, only txd0[3:0] tx_clk0 i/pd w5 mii transmit clock input: tx_en0 and txd0[3:0] are synchronous to the rising edge of this clock in 10/100base-t mode. col0 i/pd y5 collision detect: active high to indicate that there is collision occurred in half duplex mode. in full duplex mode col0 is always low. crs0 i/pd u6 carrier sense: active high if there is carrier on medium. in half duplex mode crs0 is also asserted during transmission and asynchronous to any clock. rx_dv0 i u5 receive data valid: active high to indicate that data presented on rxd0[7:0] is valid and synchronous to rx_clk0. rx_clk0 i v5 receive clock input: 125, 25 and 2.5 mhz is running at 1000/100/10 base-t mode respectively. rx_dv0 and rxd0[7:0] are synchronous to rising edge of this clock. rxd0[7:0] i/pd u4, v4, w4, y4, v3, w3, y3, w2 receive data: data received by the phy are presented on rxd0 and synchronous to rx_clk0. rxd0[3:0] is valid in 10/100/1000base-t and rxd[7:4] is valid only in 1000base-t modes. for rgmii, only rxd0[3:0] 2.1.5 rgmii/gmii/mii interface port 1 signal name i/o pin no. description gtx_clk1 o g20 125mhz clock output: please references section 2.1.1. tx_en1 o h17 transmit enable: please references section 2.1.1. txd1[7:0] o h18, h19, h20, j18, j19, j20, k19, k20 transmit data: please references section 2.1.1. tx_clk1 i/pd e17 mii transmit clock input: please references section 2.1.1.
asix electronics corporation 8 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential col1 i/pd d18 collision detect: please references section 2.1.1. crs1 i/pd d19 carrier sense: please references section 2.1.1. rx_dv1 i e19 receive data valid: please references section 2.1.1. rx_clk1 i e18 receive clock input: please references section 2.1.1. rxd1[7:0] i/pd e20, f17, f18, f19, f20, g17, g18, g19 receive data: please references section 2.1.1. 2.1.6 rgmii/gmii/mii interface port 2 signal name i/o pin no. description gtx_clk2 o a18 125mhz clock output: please references section 2.1.1. tx_en2 o b18 transmit enable: please references section 2.1.1. txd2[7:0] o c18, b19, a19, a20, b20, c19, c20, d20 transmit data: please references section 2.1.1. tx_clk2 i/pd c15 mii transmit clock input: please references section 2.1.1. col2 i/pd d15 collision detect: please references section 2.1.1. crs2 i/pd d14 carrier sense: please references section 2.1.1. rx_dv2 i a15 receive data valid: please references section 2.1.1. rx_clk2 i b15 receive clock input: please references section 2.1.1. rxd2[7:0] i/pd d16, c16, b16, a16, d17, c17, b17, a17 receive data: please references section 2.1.1. 2.1.7 rgmii/gmii/mii interface port 3 signal name i/o pin no. description gtx_clk3 o a11 125mhz clock output: please references section 2.1.1. tx_en3 o c12 transmit enable: please references section 2.1.1. txd3[7:0] o b12, a12, c13, b13, a13, c14, b14, a14 transmit data: please references section 2.1.1. tx_clk3 i/pd d9 mii transmit clock input: please references section 2.1.1. col3 i/pd c8 collision detect: please references section 2.1.1. crs3 i/pd d8 carrier sense: please references section 2.1.1. rx_dv3 i b9 receive data valid: please references section 2.1.1. rx_clk3 i c9 receive clock input: please references section 2.1.1. rxd3[7:0] i/pd a9, d10, c10, b10, a10, d11, c11, b11 receive data: please references section 2.1.1. 2.1.8 rgmii/gmii/mii interface port 4 signal name i/o pin no. description gtx_clk4 o a5 125mhz clock output: please references section 2.1.1. tx_en4 o b5 transmit enable: please references section 2.1.1.
asix electronics corporation 9 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential txd4[7:0] o c6, b6, a6, c7, b7, a7, b8, a8 transmit data: please references section 2.1.1. tx_clk4 i/pd b1 mii transmit clock input: please references section 2.1.1. col4 i/pd c1 collision detect: please references section 2.1.1. crs4 i/pd c2 carrier sense: please references section 2.1.1. rx_dv4 i b2 receive data valid: please references section 2.1.1. rx_clk4 i a1 receive clock input: please references section 2.1.1. rxd4[7:0] i/pd a2, b3, a3, c4, b4, a4, d5, c5 receive data: please references section 2.1.1. 2.2 miscellaneous signal name i/o pin no. description nc l1, l2, l3, m2, m3, m4, n1, n2, n3, p1, p2, p3, r1,r2, r3, r4 ,t3, t4, f4, f3, g2, e1, h3,g3, c3, g1,y9,v8, w8, y8, v7, w7, y7, v6, w6, y6,u11,v12,u 12,w11,v11, y11, u10, v10 w10, y10 u9, v9, w9,y15,u14, v14, w14, y14, v13, w13,y13, w12, y12,w18,y19, w19,v17,y18, w17, y17, u16, v16, w16, y16, v15, w15,t20,u17, u18, u19, u20, v18, v19, v20, w20, y20,p17,n20, n19,p19,p18, p20, r17, r18, r19, r20, t17, t18, t19 nc e_8051_en i d4 pull low, using external 8051, nc or pull hi, using internal 8051 use_83m i d3 system clock enable,0:use sysclk, 1:90m generate by pll
asix electronics corporation 10 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential clk_80in i l19 system clock input :85~90m f1 i m1 frequency 1 input, must pull high with 4.7k ohm resistor f2 i m19 frequency 2 input from phy 125m clock source. f2_ctl i d2 frequency 2 input enable, must pull low with 4.7k ohm resistor x_in i m20 crystal or osc 25mhz input: this is a clock source of internal pll. x_out o l20 crystal 25mhz output: this pin should be floating with single-ended external clock. /rst i d1 reset: active low mdio i/o/pu h2 station management data in/out: phy management data input and output. mdc o h1 station management data clock out: phy management clock. sdio i/o/pu j2 eeprom data in/out: eeprom serial data input and output. sdc i/o/pu j1 eeprom data clock in/out: eeprom serial clock. (note: it is output pin if the embedded mpu is active; otherwise as input pin) sid[4:0] i/pd i/pd i/pd i/up i/up f2, f1, e4, e3, e2 switch id: mpu can identify the switch and phys with this id. default is ?00011b?. gpio[4:0] i/o/pu k3, k2, k1, j4, j3 general purpose i/o: the 5 gpios can be programmed for special application. (note: the function is not released to user normally. please contact with asix directly if any requirement) vdd33 p d6, d13, g4, j17, p4, u7 3.3v +/-5% supply voltage. vdd18 p d7, h4, n4, n17, u8, u13 1.8v +/-5% supply voltage. avdd18 p m17, l17, k17 1.8v +/-5% supply voltage for pll. vss p d12, j9, j10, j11, j12, k4, k9, k10, k11, k12, l4, l9, l10, l11, l12,, m9, m10, m11, m12, n18, u15, m18, l18, k18 ground
asix electronics corporation 11 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 3.0 functional description 3.1 introduction in general, the AX88655AB device is a highly integrated layer 2 switch. it supports eight 10/100/1000 ports with on-chip macs. it also supports integrated switching logic, packet queuing memory and packet storage memory. the AX88655AB is capable of routing-and-forwarding packets at wire speed on all ports regardless of packet size. it is a low cost solution for eight por ts gigabit ethernet backbone switch desi gn. no cpu interface is required; after power on reset, AX88655AB provide an auto load confi guration setting function thr ough a 2 wire serial eeprom interface to access external eeprom device, and AX88655AB can easily be configured to support trunking, qos, ieee 802.3x flow control threshold setting, broadcast storm control ...etc functions. an overview of AX88655AB?s major functional blocks is shown in fig-1. 3.2 packet filtering and forwarding process the switch use simple store-and-forwar d algorithm as packet switching method. after receives incoming packets, the packets will be stored to the embedded memory first. the AX88655AB searches in the address-lookup table with da of the packet. the packet will be forward to its destination por t, if this packet?s da hits; otherwise this packet will be broadcasted. of course, only good packets will be forward. 3.3 mac address routing, learning and aging process the switch supports 4k mac entries for switching. two- way dynamic address learni ng is performed by each good unicast packet is completely received. and linear/xor hash algorithm of the static addr ess learning is achieved by eeprom configuration. on the other hand, the routing proce ss is performed whenever the packet?s da is captured. if the da can not get a hit result, the packet is going to broadcast. only the learned address entries are sc heduled in the aging machine. if one st ation does not transmit any packet for a period of time, the belonging mac address will be kicked out from the address tabl e. the aging out time can be program automatically through the eeprom configuration. (default value is 300 seconds) 3.4 full duplex 802.3x flow control in full duplex mode, AX88655AB supports the standard flow control mechanism defined in ieee 802.3x standard. it enables the stopping of remote node transm issions via a pause frame information in teraction. when space of the packet buffer is less than the initialization setting threshold va lue, AX88655AB will send out a pause-on packet with pause time equal to ?xfff? to stop the remote node transmissi on. and then AX88655AB will send out a pause-off packet with pause time equal to zero to inform the remote node to retransmit packet if has e nough space to receive packets. 3.5 half duplex back pressure control in half duplex mode, AX88655AB provide a backpressure c ontrol mechanism to avoid dropping packets during network conjection situation. when space of th e packet buffer is less th an the initialization setting threshold value, AX88655AB will send a jam pattern in the input port when it senses an incoming packet, thus force a collision to make the remote node transmission back off and will effectively avoid dr opping packets. and then AX88655AB will not send out a jam packet any more if has enough space to receive one packet. 3.6 mii polling the AX88655AB supports phy management through the seri al mdio/mdc interface. that is, the AX88655AB access related register of phys via mdio/mdc interface af ter power on reset. the AX88655AB will periodically and continuously poll and update the link stat us and link partner?s ability which incl ude speed, duplex mode, and 802.3x flow control capable status of the connected p hy devices through mdio/mdc serial interface. 3.7 port-based qos: port-pair
asix electronics corporation 12 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential AX88655AB provides 4 port-pairs for bandwidth management. users can assign any two ports as one port-pair with internal registers basically. any packet s will put the high priority queue of th e port-pair when send the packets each other. that is, two ports of each po rt-pair will obtain more bandwidth th an other ports when congestion. in addition, one port can be as the highest priority port if one all_bit of a port-pair is active. that is, user can assign format of the port-pair as oneport-to-all and every packets of the oneport will put in the high priority transmit queue of other ports.. 3.8 vlan and broadcast storming prevention AX88655AB supports 8 port-based vlan groups to ease the administration of logical groups of stations that can communicate as if they were on the same lan, and move, add or change numbers of these groups. the scheme can prevent effectively the broa dcast storming from interfering with the whole transmission performance between ports. during this time, the ports belonging to different groups are i ndependent. only the destination port of broadcast packets in the same group will be allowed. furthermore, the sc heme of the vlan group divi ding is very flexible. the overlapped port-groups are allowed during some operations, for example, one port can be shared by two groups, and all the other operations between these two groups remain indepe ndent except for the overlapped port. only the overlapped port could use the same destination mac address for two different vlan port-groups. the AX88655AB can enable broadcast storm filtering control by maxstorm[1:0]. this allows limitation of the number of broadcast packets into the switch, and can be implemented on a per port basis. the threshold of number of broadcast packets is set to 64/32/16. when enabled (i.e., maxstorm[1:0] is not 2?b00), each port will drop broadcast packets (destination mac id is ff ff ff ff ff ff) after receiving 64 continuous broadcast packets. the counter will be reset to 0 every 1 second or when receiving any non-broadcast packets (destination mac id is not ff ff ff ff ff ff). when disabled (i.e., maxstorm[1:0] is 2?b00), or the num ber of non-unicast packets received at the port is not over the programmed threshold, the switch will forward th e packet to all the ports (except the receiving port) within the vlans specified at the receiving port. if broadcast-storm-drop is enabled, the AX88655ABb w ill only drop broadcast packets but not the multicast packets. 3.9 security operation - port sa restriction AX88655AB provides source mac address security support. when onesasecuritymode is turned on, then the port(s) will be fixed in the secured sa and stop learning. the por t(s) will forward packets with the matched sa. if any other ports receive the packet with this secures sa, this packet will be discarded. learns a source mac address again if updatesaforsecurity is turned on. 3.10 ingress/egress bandwidth control scheme the bandwidth control will set th e maximum bandwidth that each por t can support. basically AX88655AB provides 256 bandwidth classes of 1000 mbps with thresholds (resoluti oningress and resolutionengress). in half-duplex mode, the receiving side (ingress) will drop packets or send jam with igressmode if it is over the ba ndwidth threshold. on the transmitting side (egress), if it goes over the threshold, it w ill stop transmitting until time is up, then transmit data again . under full-duplex mode, if the transmitting data meet the ba ndwidth threshold, the bandwid th control scheme will send the drop packets or 802.3x pause frame. when it expires, it w ill send the release packet. fo r the receiving side without flow control (802.3x), it will drop the p acket if it goes over the threshold. 3.11 port mirroring port mirroring is a function that mirrors or duplicates traffic from one ?target port? to a ?mirror port?. the mirror or target port mirroring can be set up for each port individually to mirror either incoming packets or outgoing packets. incoming and outgoing traffic need not be mirrored to the same port. unidirectional traffic on a port can only be mirrored to one mirror port. only correct packets that would normally be handled by the AX88655AB will be mirrored. packets with crc errors and collision fragments etc are not mirrored. - input mirroring: traffic received on a port will be sent to the mirro r port as well as to any other addressed port. - output mirroring: traffic sent out on a port will also be sent to the mirror port.
asix electronics corporation 13 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 4.0 register descriptions register tables summary: address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default 00 h reserved reserved 0000 h 01 h reserved reserved ffff h 02 h reserved + rxflowctrl[4:0] reserved + txflowctrl[4:0] 0000 h 03 h reserved reserved 00ff h 04 h reserved reserved 00ff h 05 h reserved 0000 h 06 h reserved reserved 00ff h 07 h reserved reserved 1215 h 08 h reserved reserved reserved reserved 7777 h 09 h reserved reserved reserved reserved 7777 h 0a h portpair1[4:0] portpair0[4:0] 0000 h 0b h portpair3[4:0] portpair2[4:0] 0000 h 0c h lowqueueweight[3:0] reserve d lw_lowqueuediscardlimit [9:0] 1060 h 0d h highqueueweight[3:0] maxstorm[1:0] lw_highqueuediscardlimit [9:0] 1060 h 0e h res pto res mps[1:0] sr sp nsb res 51te res qos[1:0] ae hm db 8880 h 0f h reserved maxage[8:0] 1865 h 10 h trunk47[2:0] trunk30[2:0] reserved 00c0 h 11 h res res reserved lowqueueflowctrlmark[9:0] 0010 h 12 h maxjam[5:0] highqueueflowctrlmark[9:0] 2810 h 13 h reserved hw_lowqueuediscardlimit[9:0] 0070 h 14 h res smartfc [1:0] res reserv ed hw_highqueuediscardlimit[9:0] 0070 h 15 h port-based vlan group #1 port-based vlan group #0 0000 h 16 h port-based vlan group #3 port-based vlan group #2 0000 h 17 h reserved port-based vlan group #4 0000 h 18 h reserved reserved 0000 h 19 h resolutioningress port 1[7:0] resolutioningress port 0[7:0] ffff h 1a h resolutioningress port 3[7:0] resolutioningress port 2[7:0] ffff h 1b h reserved resolutioningress port 4[7:0] ffff h 1c h reserved reserved ffff h 1d h iso rm mirrorport[2:0] portmirroren[ 1:0] ingressmode resolutionengress port 7[7:0] 00ff h 1e h reserved + updatesaforsecurity[4:0] reserved + onesasecuritymode[4:0] 0000 h 1f h gclk125mhz_dly1ns_n[7:0] targetport[2:0] jumboleng13_10[3:0] jumboenable 0000 h note: 1. the word ?reserved? = ?res.? on the above table. 2. care must be taken that the ?reserved? registers should keep the default value always. change of any reserved value may be resulting in unpredictable conditions. 3. the registers can be accessed by inte rnal mpu only. the mpu will read in configuration table, located on eeprom at somewhere address, and programs the above register s when every time power on or after system reset. 4. basically, the registers can be accessed with the same data format as station management (similar to mdc and mdio) via adc and adio pins. ]
asix electronics corporation 14 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 4.1 register 00 bit r/w description 15:8 r/w reserved 7:0 r/w reserved 4.2 register 01 bit r/w description 15:8 r/w reserved 7:0 r/w reserved 4.3 register 02 bit r/w description 15:12,8 r/w flowctrlenable for mac?s receive part of po rt[4:0] are configured by int. or ext. 8051 0: not identify pause frames by receive part of mac 1: can identify pause frames. that is, pausetimer of mac will be active. 7:4,0 r/w flowctrlenable for mac?s transmit part of port[4:0] are configured by int. or ext. 8051 0: not send pause frames 1: send pause frames when the packet buffer run out. 4.4 register 03 bit r/w description 15:8 r/w reserved 7:0 r/w reserved 4.5 register 04 bit r/w description 15:8 r/w reserved 7:0 r/w reserved 4.6 register 05 bit r/w description 15:0 r reserved 4.7 register 06 bit r/w description 15:10 r/w reserved 9:0 r/w reserved 4.8 register 07 bit r/w description 15 r/w reserved 14:8 r/w reserved 7 r/w reserved 6:0 r/w reserved
asix electronics corporation 15 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 4.9 register 08 bit r/w description 15:12 r/w reserved 11:9 r/w reserved 8:4 r/w reserved 3:0 r/w reserved 4.10 register 09 bit r/w description 15:12 r/w reserved 11:9 r/w reserved 8:4 r/w reserved 3:0 r/w reserved 4.11 register 0a bit r/w description 15 r/w all_bit of portpair #1 when qos[0] is high 14:12 r/w port_id of portpair #1 when qos[0] is high 11 r/w all_bit of portpair #1 when qos[0] is high 10:8 r/w port_id of portpair #1 when qos[0] is high 7 r/w all_bit of portpair #0 when qos[0] is high 6:4 r/w port_id of portpair #0 when qos[0] is high 3 r/w all_bit of portpair #0 when qos[0] is high 2:0 r/w port_id of portpair #0 when qos[0] is high
asix electronics corporation 16 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 4.12 register 0b bit r/w description 15 r/w all_bit of portpair #3 when qos[0] is high 14:12 r/w port_id of portpair #3 when qos[0] is high 11 r/w all_bit of portpair #3 when qos[0] is high 10:8 r/w port_id of portpair #3 when qos[0] is high 7 r/w all_bit of portpair #2 when qos[0] is high 6:4 r/w port_id of portpair #2 when qos[0] is high 3 r/w all_bit of portpair #2 when qos[0] is high 2:0 r/w port_id of portpair #2 when qos[0] is high 4.13 register 0c bit r/w description 15:12 r/w weightforlowque: weight for low priority queues when qos is active (see appendix c) 11:10 r/w reserved 9:0 r/w lowwatermark of low priority queues when drop packets 4.14 register 0d bit r/w description 15:12 r/w weightforhighque: weight for high priority queues when qos is active (see appendix c) 11:10 r/w maximum number of broadcast frames that can be accumulated in each input frame buffer. 00: disable broadcast storm control 01: 31 frames 10: 47 frames 11: 63 frames 9:0 r/w lowwatermark of high priority queues when drop packets 4.15 register 0e bit r/w description 15 ro reserved 14 r/w 802.3x flow control frame recognition control 0: check for mac control frame da mac address in addition to the mac control type field 1: check only the mac control type field 13 r/w setting for maximum length of packet that received 0: 1518 byte 1: 1522 byte 12:11 r/w reserved 10 r/w software reset (only reset the switch kernel) 0: active 1: disable 9 r/w back-off algorithm selection 0: disable. device will perform the ieee sta ndard exponential back off algorithm when a collision occurs. 1: enable. when collisions occur, the macs will back off up to 7 slots. note :: supermac v.s. flowctrl 8 r/w 0: stop generate jam patterns after some collision that is defined by maxjam[5:0] 1: never stop back-pressure (note: only availible for ethernet..not fasteternet) 7 r/w reserved 6 r/w reserved
asix electronics corporation 17 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 5 r/w reserved 4:3 r/w qos selection 00: disable qos function 01: port-pair priority algorithm 10: 802.1p 2 r/w agingenable switch table entry aging control. only the dynamically learned addresses will be aged. all explicit entries will not age. the aging time is programmed in register 0f. 0: disable. the table aging process is disabled. 1: enable. the table aging process is en abled and a hardware process ages every dynamically learned table entry. 1 r/w hash algorithm selection 0: xor mapping 1: linear mapping 0 r/w reserved 4.16 register 0f bit r/w description 15:9 r/w ipg1 for transmit part of all mii macs 8:0 r/w maxage. this is a seven-bit register cont aining unsigned integer for determining the address-aging timer. 4.17 register 10 bit r/w description 15:13 r/w trunking selection for port[7:4] 000: disable trunking 001: disable trunking 010: one 2-port trunking for port[5:4] 011: one 2-port trunking for port[5:4] 100: one 2-port trunking for port[7:6] 101: one 4-port trunking 110: two 2-port trunkings for port[7:6] and port[5:4] 111: one 4-port trunking 12:10 r/w trunking selection for port[3:0] 000: disable trunking 001: disable trunking 010: one 2-port trunking for port[1:0] 011: one 2-port trunking for port[1:0] 100: one 2-port trunking for port[3:2] 101: one 4-port trunking 110: two 2-port trunkings for port[3:2] and port[1:0] 111: one 4-port trunking 9:0 r/w reserved 4.18 register 11 bit r/w description 15:10 r/w reserved 9:0 r/w lowwatermarkforflowctrl. this is a ten-bit register containing unsigned integer for low priority queues whether generate pause-on or not.
asix electronics corporation 18 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 4.19 register 12 bit r/w description 15:10 r/w maxjam. this is a six-bit register containing unsigned integer for determining the jam counter whether generate jam or not. 9:0 r/w highwatermarkforflowctrl. this is a ten- b it register containing unsigned integer for high priority queues whether generate pause-off or not. 4.20 register 13 bit r/w description 15:10 r/w reserved 9:0 r/w highwatermark of low priority queues when drop packets 4.21 register 14 bit r/w description 15 r/w reserved 14:13 r/w smartflowctrl for mix-speed connection 0: disable 1: disable flow ctrl for all 10 mbps port 2: disable flow ctrl for all 100 mbps port 3: reserved 12 r/w reserved 11:10 r/w reserved 9:0 r/w highwatermark of high priority queues when drop packets 4.22 register 15 bit r/w description 15:8 r/w vlan #1 7:0 r/w vlan #0 4.23 register 16 bit r/w description 15:8 r/w vlan #3 7:0 r/w vlan #2 4.24 register 17 bit r/w description 15:8 r/w reserved 7:0 r/w vlan #4
asix electronics corporation 19 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 4.25 register 18 bit r/w description 15:8 r/w reserved 7:0 r/w reserved 4.26 register 19 bit r/w description 15:8 r/w resolution of port #1 for ingress bandwidth control 7:0 r/w resolution of port #0 for ingress bandwidth control 4.27 register 1a bit r/w description 15:8 r/w resolution of port #3 for ingress bandwidth control 7:0 r/w resolution of port #2 for ingress bandwidth control 4.28 register 1b bit r/w description 15:8 r/w reserved 7:0 r/w resolution of port #4 for ingress bandwidth control 4.28 register 1c bit r/w description 15:8 r/w reserved 7:0 r/w reserved 4.28 register 1d bit r/w description 15 r/w isolation enable for port-based mirror 0: disable 1: active 14 r/w resolutionmode 0: byte mode 1: word mode 13:11 r/w mirror port for port-based mirror 10:9 r/w port-based mirror mode 0: disable port-based mirror 1: imgress 2: egress 3: reserved 8 r/w igress mode 0: drop pkts by arl 1: send pause for gmactx 7:0 r/w resolution of port #7 for egress bandwidth control
asix electronics corporation 20 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 4.28 register 1e bit r/w description 15:12,8 r/w update source mac for security mode of each port 0: keep one source mac 1: update the source mac 7:4,0 r/w onesasecuritymode[4:0] 0: disable 1: active 4.28 register 1f bit r/w description 15:12,8 r/w gclk125mhz_dly_1ns_n[4:0] 0: delay 1ns 1: no delay 7:5 r/w target port for port-based mirror 4:1 r/w max length of jumbo packet: from 1k to 15k byte 0 r/w accept jumbo enable 0: drop jumbo packets 1: accept jumbo packets
asix electronics corporation 21 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 5.0 electrical specification and timing 5.1 absolute maximum ratings description sym min max units operating temperature ta 0 +70 c storage temperature ts -55 +150 c supply voltage vcc -0.3 +4.0 v input voltage vin -0.3 vdd+0.5 v output voltage vout -0.3 vdd+0.5 v lead temperature (soldering 10 seconds maximum) tl -55 +220 c note: stress above those listed under absolute maximum rati ngs may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability 5.2 general operation conditions description sym min max units operating temperature ta 0 +70 c supply voltage vdd +3.0 +3.6 v 5.3 dc characteristics (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 70 c) description sym min max units low input voltage vil vss-0.3 0.8 v high input voltage vih 2 vdd+0.5 v low output voltage vol 0.4 v high output voltage voh 2.4 v input leakage current 1 (note 1) iil1 10 ua input leakage current 2 (note 2) iil1 500 ua output leakage current iol 10 ua description sym min tpy max units power consumption pc tbd ma note: 1. all the input pins without pull low or pull high. 2. those pins had been pull low or pull high.
asix electronics corporation 22 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 5.4 ac specifications 5.4.1 lclk lclk/x25m_i tr tf tlow clk25m_o tod symbol description min typ. max units tcyc cycle time 20 ns thigh clk high time 8 10 12 ns tlow clk low time 8 10 12 ns tr/tf clk slew rate 1 - 4 ns tod lclk to bmclk out delay 2 ns 5.4.2 reset timing ref_clk /rst symbol description min typ. max units trst reset pulse width 10 - - ref_clk tcyc thigh
asix electronics corporation 23 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 5.4.3 gmii interface timing tx & rx tx : rx: symbol description min typ. max units t0 ref_clk clock cycle time 7.998 8 8.002 ns t1 ref_clk clock high time 4 ns t2 tx_en and txd data setup to ref_clk rising edge 2.5 ns t3 tx_en and txd data hold from ref_clk rising edge 0.5 ns t4 rx_dv and rxd data setup to rx_clk rising edge (rcvr) 2.0 ns t5 rx_dv and rxd data hold from rx_clk rising edge(rcvr) 0 ns gtxcl k t0 t1 tx_en txd [7:0] t2 t3 rx_clk rx_dv rxd [7:0] t4 t5
asix electronics corporation 24 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 5.4.4 100 mbps mii interface timing tx & rx symbol description min typ. max units t0 tx_clk cycle time 39.996 40 40.004 ns t1 tx_clk high time 14 20 26 ns t2 tx_en delay from txclk high 7.440 21.760 ns t3 txd delay from tx_clk high 3.410 13.320 ns t4 t5 rx_clk crs t6 rx_dv t7 rxd symbol description min typ. max units t4 rx_clk clock cycle time 39.996 40 40.004 ns t5 rx_clk clock high time 14 20 26 ns t6 crs to rx_dv delay requirement 40 160 ns t7 rxd or rx_dv setup to rx_clk rise time 10 ns txclk t0 t1 tx_en txd [7:0] t2 t3
asix electronics corporation 25 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 5.4.5 10 mbps mii interface timing tx & rx t0 t1 tx_clk t2 t2 tx_en t3 t3 txd symbol description min typ. max units t0 tx_clk cycle time 399.96 400 400.04 ns t1 tx_clk high time 14 20 26 ns t2 tx_en delay from tx_clk high 7.440 21.760 ns t3 txd delay from tx_clk high 3.410 13.320 ns t4 t5 rxclk crs t6 rxdv t7 rxd rxer symbol description min typ. max units t4 rx_clk clock cycle time 39.996 40 40.004 ns t5 rx_clk clock high time 14 20 26 ns t6 crs to rx_dv delay requirement 40 160 ns t7 rxd or rx_dv setup to rx_clk rise time 10 ns
asix electronics corporation 26 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 5.4.1 rgmii interface timing
asix electronics corporation 27 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential 6.0 package information
asix electronics corporation 28 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential
asix electronics corporation 29 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential
asix electronics corporation 30 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential appendix a: system applications a.1 AX88655AB as 5-port soho high traffic power user switch a.2 AX88655AB as 5-port smart switch (dip switch configurable) AX88655AB switch controller quad gmii phy or 4 r/gmii phys gmii phy or 1 r/gmii phys seeprom for save configuration i/o port for configuration from pc AX88655AB switch controller eeprom 5 * 10/100/1000mbps phys configuration serial in leds or general serial output dip sw
asix electronics corporation 31 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential appendix b: design note b.1 using mii i/f connects to mac using mii interface to connect to mac type device application for AX88655AB is illustrated bellow. 10k gnd AX88655AB / switch ax88195 / mac note: 1. the mac needs to run at full-duplex mode. 2. care must be taken that the receive side has enough setup and/or hold time 3. some kind of cpu with embedded mac can also refer to this example col0 tx_en0 tx_clk0 txd0[3:0] crs0 rx_dv0 rx_clk0 rxd0[3:0] col crs rx_dv rx_clk rxd[3:0] rx_er tx_en tx_clk txd[3:0] tx_er 25mhz clock
asix electronics corporation 32 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential appendix c: weight setting for qos service ratio (high : low) weightforhighque[3:0] weightforlowque[3:0] 1 : 1 4?b0100 4?b0100 2 : 1 4?b0100 4?b0010 3 : 1 4?b0110 4?b0010 4 : 1 4?b0100 4?b0001 5 : 1 4?b0101 4?b0001 6 : 1 4?b0110 4?b0001 7 : 1 4?b0111 4?b0001 8 : 1 4?b1000 4?b0001 9 : 1 4?b1001 4?b0001 10 : 1 4?b1010 4?b0001 11 : 1 4?b1011 4?b0001 12 : 1 4?b1100 4?b0001 13 : 1 4?b1101 4?b0001 14 : 1 4?b1110 4?b0001 15 : 1 4?b1111 4?b0001 appendix d: resolution ingress/egress for bandwidth control gigabit bandwidth ratio resolutioningress / resolutionengress 10% 8?h1a 20% 8?h34 30% 8?h4e 40% 8?h67 50% 8?h80 60% 8?h9a 70% 8?hb4 80% 8?hc0 90% 8?he7 100% 8?hff note : 1. resolutionmode is ?byte mode?. 2. 256 level of bandwidth control supports.
asix electronics corporation 33 AX88655AB 5-port 10/100/1000base-t ethernet switch confidential revision date comment v. 0.5 11/07/02 initial release. v. 0.6 02/01/03 modify x_in clock from 27 to 25 and system clock from 90m to 83.3m register 0d modify v. 0.7 2003/4/7 1. appendix d resolutions setting on 30% (change from 34 to 4e) 2. change pin name from nc to new name: pin # new pin name d4 e_8051_en m19 f2 l19 clk_80_in d3 use_83m d2 f2_ctl m1 f1 3. modify system clock to 90m v. 0.8 2003/6/11 1. add rgmii timing diagram 2. trunking register correction 3. modify all gmii/mii to rgmii/gmii/mii 4f, no.8, hsin ann rd., science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-5799500 fax: 886-3-5799558 email: support@asix.com.tw web: http://www.asix.com.tw

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